1. Field of the Invention
This invention relates generally to digital filtering. More particularly, it relates to an efficient decimation filter architecture and method for particular use with polyphase input samples such as quadrature samples.
2. Background of Related Art
Meeting timing constraints in very large scale integration (VLSI) design is a major challenge for today""s high speed communications receivers. As speeds increase, less time is available to perform given tasks. This is particularly true in the case of digital filtering.
For instance, a conventional half rate finite impulse response (FIR) digital filter 600 is depicted in FIG. 6. The xe2x80x98half ratexe2x80x99 of the shown FIR filter 600 refers to the decimation of an input data rate by one half with respect to an output data rate.
FIG. 7 shows a block diagram of the half rate FIR filter 600 shown in FIG. 6.
In particular, a conventional FIR filter includes a delay chain 699, a uniphase math logic module 620, and filtered (i.e., decimated) output samples 630.
As is conventionally known, the delay chain 699 comprises twelve individual register or storage phases 601-612 each corresponding to a delay in an input sample. In operation, samples are input to the first register 601 and ripple serially through the delay chain 699 until exiting the last, twelfth register phase 612. Thus, samples input to the first register 601 eventually ripple through the delay chain 699 toward the last register 612 as new samples are input to the delay chain 699.
The values stored in each of the registers 601 through 612 during any particular sample cycle are input to a uniphase math logic module 620. The uniphase math logic module 620 performs the additions and multiplications necessary to perform a finite impulse response filtering function. The results of the mathematics performed in the uniphase math logic module 620 are registered and output as decimated output samples 630.
FIG. 8 shows a more detailed schematic of the FIR filter 600 shown in FIGS. 6 and 7.
In particular, FIG. 8 shows that each register 601-612 is comprised of two sets of serially connected registers or storage elements clocked by a data clock. Each register latches input data at an input terminal D when enabled and clocked, and outputs that data when clocked by the system clock signal. Each register 601-612 is enabled when a particular logic level (e.g., logic high) is present on its respective enable E input.
The conventional FIR filter 600 is adequate for low speed operations, e.g., less than about 50 megahertz (MHz), but experiences deteriorated performance at high speeds. This is most notably because of the limitations in sample width caused by the maximum number of bits which can ripple through any particular serial element, e.g., an adder within any given period of time.. For instance, as speeds approach 75 MHz and the. corresponding cycle time approaches about 13 nanoseconds (nS), sufficient time is not available for all of the bits of a larger sample or subproduct to ripple through from a most significant bit (MSB) to a least significant bit (LSB), or from an LSB to an MSB.
For instance, based on these speeds and presuming it takes about 1 nS or so for each bit in a multiple serial bit element such as an adder to ripple any carry and/or sign bits, and thus the FIR filter 600 becomes limited to a sample or product size corresponding to the amount of time available, e.g., to about 13 bits corresponding to the available 13 nS if operated at 75 MHz. Unfortunately, subproducts in a conventional FIR filter 600 such as is shown in FIGS. 6 to 8 may become lengthy, e.g., 27 bits as shown at 802, 804 in FIG. 8, and will thus not be capable of rippling through all 27 bits in the adder function 806 at such high clock speeds. Accordingly, as speeds increase, FIR filtering becomes limited in sample and subproduct length and thus eventually becomes quite limited using conventional technology.
There is thus a need for an architecture and method of FIR filtering which is capable of operation at higher speeds, e.g., speeds in excess of 75 MHz.
In accordance with the principles of the present invention, a digital filter comprises an odd/even digital delay line comprising a plurality of register phases, a first sub-plurality of every other one of the plurality of register phases receiving a first sample stream, and a second sub-plurality of the other every other one of the plurality of register phases receiving a second sample stream. The odd/even digital delay line alternates in a serial direction between one of odd and even register phases receiving samples from the first sample stream, and the other of the odd and even register phases receive samples from the second sample stream. A polyphase math logic module is adapted to receive samples from a plurality of tap points along the odd/even digital delay line.
A method of decimating a polyphase signal in accordance with the principles of the present invention comprises receiving a sample stream containing samples each based on one of a plurality of phases of a common signal. Odd samples in the sample stream are delayed in a first plurality of serially connected digital register phases, and even samples are delayed in the sample stream in a second plurality of serially connected digital register phases. The delayed odd samples and the delayed even samples are alternately filtered to provide a decimated polyphase signal.